Buried Trench Isolation in Integrated Circuits

ABSTRACT

A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 14/207,303, filed Mar. 12, 2014, which is related to U.S.application Ser. Nos. 14/048,527, and 14/048,863, all of which areincorporated by reference herein in their entireties.

BACKGROUND

1. Field

The present application relates to the fabrication of trenches buried insubstrates of integrated circuits.

2. Background

With the advances in semiconductor technology, there has been increasingdemand for higher storage capacity, faster processing systems, and highspeed communication systems. To meet these demands, the semiconductorindustry continues to scale down dimension of devices, and also increasepacking density of devices on an integrated circuit (IC) to accommodatea larger number of devices on an IC. However, scaling down of devices tosmaller dimensions can introduce short channel effects in the devicesdue to the short channel lengths (about approximately 100 nm or less) ofthe scaled down devices. In addition, closely spaced devices may sufferfrom disturbances such as electron leakage, noise coupling, orelectrostatic coupling. These drawbacks can degrade the operatingcharacteristics and performance of the devices over time. Thus, it isdesirable to improve performance of devices in such high density ICs.

SUMMARY

According to an embodiment, an IC includes a substrate, a first deviceand a second device, that may exist next to each other, and are formedon a surface of the substrate. Each of the first and the second devicesinclude a gate structure. The IC further includes an isolator formedwithin the substrate and positioned space-wise between the first and thesecond device. The isolator includes one or more cavities buried underthe substrate to isolate the two devices. In an embodiment the one ormore cavities comprises one cavity and the one cavity is filled with adielectric material.

According to another embodiment, a method for fabricating an integratedcircuit (IC) is provided. The method includes forming a trench in asubstrate. The trench having a closed end within the substrate and anopen end adjacent a surface of the substrate. The method furtherincludes initiating a reshaping of portion of the substrate surroundingthe open end of the trench. The method further includes closing the openend of the trench with substrate martial to form an isolation regionwithin the substrate. The method further includes creating first andsecond devices on the surface of the substrate on opposite sides of theisolation region.

According to another embodiment, a method for fabricating an IC isprovided. The method includes forming a trench in a substrate. Themethod further includes depositing dielectric material in the trenchsuch that the layer of dielectric material substantially fills thetrench. The method further includes removing the dielectric materialfrom a top portion of the trench. The method further includes closingthe open end of the trench such that the substrate material fills thetop portion of the trench.

Further features and advantages of the present disclosure, as well asthe structure and operation of various embodiments of the presentdisclosure, are described in detail below with reference to theaccompanying drawings. It is noted that the present disclosure is notlimited to the specific embodiments described herein. Such embodimentsare presented herein for illustrative purposes only. Additionalembodiments will be apparent to persons skilled in the relevant art(s)based on the teachings contained herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate the present disclosure and,together with the description, further serve to explain the principlesof the disclosure and to enable one skilled in the pertinent art to makeand use the disclosure.

FIGS. 1A-1C each illustrate a cross-sectional view of an IC, accordingto an embodiment.

FIGS. 2A-2E illustrates a cross-sectional view of an IC including aburied trench at select stages of its fabrication process, according toan embodiment.

FIGS. 3A-3C illustrates a cross-sectional view of an IC including aburied trench at select stages of its fabrication process, according toan embodiment.

FIGS. 4A-4C illustrates a cross-sectional view of an IC including aincluding a buried trench at select stages of its fabrication process,according to an embodiment.

FIGS. 5A-5E illustrate cross-sectional views of an IC including one ormore buried trenches at select stages of its fabrication process,according to an embodiment.

FIG. 6 illustrates a flowchart for a method of fabricating an IC,according to a first embodiment.

FIG. 7 illustrates a flowchart for a method of fabricating an IC,according to a second embodiment.

The present disclosure will now be described with reference to theaccompanying drawings. In the drawings, like reference numbers generallyindicate identical or similar elements. Additionally, generally, theleft-most digit(s) of a reference number identifies the drawing in whichthe reference number first appears.

DETAILED DESCRIPTION

The following Detailed Description refers to accompanying drawings toillustrate embodiments consistent with the disclosure. The embodiment(s)described, and references in the specification to “one embodiment,” “anembodiment,” “an example embodiment,” etc., indicate that theembodiment(s) described may include a particular feature, structure, orcharacteristic, but every embodiment may not necessarily include theparticular feature, structure, or characteristic. Moreover, such phrasesare not necessarily referring to the same embodiment. Further, when aparticular feature, structure, or characteristic is described inconnection with an embodiment, it is understood that it is within theknowledge of one skilled in the art to effect such feature, structure,or characteristic in connection with other embodiments whether or notexplicitly described.

The embodiments described herein are provided for illustrative purposes,and are not limiting. Other embodiments are possible, and modificationsmay be made to the embodiments within the spirit and scope of thedisclosure. Therefore, the Detailed Description is not meant to limitthe present disclosure. Rather, the scope of the present disclosure isdefined only in accordance with the following claims and theirequivalents.

The following Detailed Description of the embodiments will so fullyreveal the general nature of the present disclosure that others can, byapplying knowledge of those skilled in relevant art(s), readily modifyand/or adapt for various applications such exemplary embodiments,without undue experimentation, without departing from the spirit andscope of the disclosure. Therefore, such adaptations and modificationsare intended to be within the meaning and plurality of equivalents ofthe exemplary embodiments based upon the teaching and guidance presentedherein. It is to be understood that the phraseology or terminologyherein is for the purpose of description and not of limitation, suchthat the terminology or phraseology of the present specification is tobe interpreted by those skilled in relevant art(s) in light of theteachings herein.

Those skilled in the relevant art(s) will recognize that thisdescription may be applicable to many various semiconductor devices, andshould not be limited to any particular type of semiconductor devices.Before describing the various embodiments in more detail, furtherexplanation shall be given regarding certain terms that may be usedthroughout the descriptions.

In embodiments, the term “etch” or “etching” or “etch-back” generallydescribes a fabrication process of patterning a material, such that atleast a portion of the material remains after the etch is completed. Forexample, generally the process of etching a semiconductor materialinvolves the steps of patterning a masking layer (e.g., photoresist or ahard mask) over the semiconductor material, subsequently removing areasof the semiconductor material that are no longer protected by the masklayer, and optionally removing remaining portions of the mask layer.Generally, the removing step is conducted using an “etchant” that has a“selectivity” that is higher to the semiconductor material than to themask layer. As such, the areas of semiconductor material protected bythe mask would remain after the etch process is complete. However, theabove is provided for purposes of illustration, and is not limiting. Inanother example, etching may also refer to a process that does not use amask, but still leaves behind at least a portion of the material afterthe etch process is complete.

The above description serves to distinguish the term “etching” from“removing.” In an embodiment, when etching a material, at least aportion of the material remains behind after the process is completed.In contrast, when removing a material, substantially all of the materialis removed in the process. However, in other embodiments, ‘removing’ mayincorporate etching.

In an embodiment, the terms “deposit” or “dispose” describe the act ofapplying a layer of material to the substrate. Such terms are meant todescribe any possible layer-forming technique including, but not limitedto, thermal growth, sputtering, evaporation, chemical vapor deposition,epitaxial growth, atomic layer deposition, electroplating, etc.

In an embodiment, the term “substrate” describes a material onto whichsubsequent material layers are added. In embodiments, the substrateitself may be patterned and materials added on top of it may also bepatterned, or may remain without patterning. Furthermore, “substrate”may be any of a wide array of semiconductor materials such as silicon,germanium, gallium arsenide, indium phosphide, etc. In otherembodiments, the substrate may be electrically non-conductive such as aglass or sapphire wafer.

In an embodiment, the term “substantially perpendicular,” in referenceto a topographical feature's sidewall, generally describes a sidewalldisposed at an angle ranging between about 85 degrees and 90 degreeswith respect to the substrate.

In an embodiment, the term “substantially in contact” means the elementsor structures in substantial contact can be in physical contact witheach other with only a slight separation from each other.

In an embodiment, devices fabricated in and/or on the substrate may bein several regions of the substrate, and these regions may not bemutually exclusive. That is, in some embodiments, portions of one ormore regions may overlap.

An Integrated Circuit According to a First Embodiment

FIG. 1A illustrates a cross-sectional view of an IC 100 a according toan embodiment. In one example, IC 100 a may include a substrate 102, oneor more devices 101, and a trench 104 (e.g., a buried trench). Devices101 as shown in FIG. 1 include only two devices 101 a and 101 b for thesake of simplicity. However, as would be understood by a person ofskilled in the art based on the description herein, devices 101 mayinclude any number of devices.

Substrate 102 may be a silicon (Si) substrate implanted with p-typecarriers to be a p-type Si substrate, according to an exampleembodiment. The p-type carriers may be provided by p-type materials,such as, but not limited to, boron. Alternatively, substrate 102 may bea p-type well formed in an n-type Si substrate or well (not shown). TheN-type Si substrate is formed by implanting n-type carriers that areprovided by n-type materials, such as, but not limited to, phosphorus.

In an example, devices 101 a and 101 b may each represent a field-effecttransistor (FET) including doped regions and a gate structure (notshown). Devices 101 a and 101 b may be similar in structure andfunction. Alternatively, devices 101 a and 101 b may be two distinctdevices. According to an embodiment, devices 101 may be positioned on atop surface 102 a of substrate 102.

In one example, buried trench 104 may be filled with a dielectricmaterial. The dielectric material may be, for example, oxide or nitride.

In accordance with an embodiment, buried trench 104 may be positioned insubstrate 102 between devices 101 a and 101 b. While buried trench 104is shown in FIG. 1A—to comprise a vertical cross-section having arectangular perimeter. In alternate embodiments buried trench 104 maycomprise vertical cross-sections having any geometric shaped perimeters(e.g., trapezoidal).

Buried trench 104 may run parallel to a bitline or the substrate surface102, and it may have a greater depth than width, in an embodiment. In anexample, buried trench 104 may comprise a vertical dimension of about100 nm-400 nm and it may be positioned about 100 nm or less under thesurface 102 a of substrate 102.

During operation of devices 101, electronic processes may be carried outwithin a region of substrate 102. These electronic processes of device101 a may create disturbances such as, but not limited to, currentleakage, noise coupling, or electrostatic coupling that may negativelyaffect the electronic processes and as a result the performance ofadjacent device 101 b in instances where devices 101 are closely spacedon substrate 102. In such instances, buried trench 104 may provideelectrical isolation between the electronic processes of devices 101 aand 101 b within substrate 102, according to an embodiment.

It should be noted that IC 100 is shown in FIG. 1A as including only onearrangement of buried trench 104 interposed between adjacent devices 101a and 101 b for the sake of simplicity. However, as would be understoodby a person of skilled in the art based on the description herein, IC100 may include any number of such arrangements with devices and buriedtrenches similar to devices 101 and buried trench 104, respectively. Inaddition, IC 100 may include other devices and functional units that arenot shown for the sake of simplicity.

An Integrated Circuit According to a Second Embodiment

FIG. 1B illustrates a cross-sectional view of an IC 100 b according toan embodiment. IC 100 b is similar to IC 100 a as described above,therefore only differences between IC 100 a and 100 b are describedherein.

IC 100 b may include buried trench 105. Buried trench 105 may be acavity that is empty, i.e., without any solid material. The buriedtrench 105 may, for example, contain air.

An Integrated Circuit According to a Third Embodiment

FIG. 1C illustrates a cross-sectional view of an IC 100 c according toan embodiment. IC 100 c is similar to IC 100 a as described above,therefore only differences between IC 100 a and 100 c are describedherein.

In one example, IC 100 c may include multiple buried trenches 106. Inthe example embodiment shown in FIG. 1C, buried trenches 106 includescavities 106 a, 106 b, and 106 c which are arranged substantiallyvertically. Buried trenches 106 as shown in FIG. 1C include threecavities for the sake of simplicity. However, as would be understood bya person of skilled in the art based on the description herein, buriedtrenches 106 may include any number of cavities.

In an embodiment, buried trenches 106 are cavities empty of any solidmaterial. The buried trenches 104 may, for example, contain air.

An Example Method for Fabricating an Integrated Circuit According to aFirst Embodiment

FIGS. 2A-2E illustrate cross-sectional views of partially fabricated IC100 a during formation of buried trench 104, according to an embodiment.For the sake of simplicity, devices 101 are not shown in the figures forillustrating example methods of forming a buried trench. In someembodiments, devices 101 may be fabricated before forming a buriedtrench. In some other embodiments, devices 101 may be fabricated afterforming a buried trench.

FIG. 2A illustrates a cross-sectional view of a partially fabricated IC100 a after formation of trench 202 in substrate 102. Trench 202 may beformed by any conventional etching methods suitable for etching thematerial of substrate 102. For example, a dry etch process such as, butnot limited to, reactive ion etching (RIE) may be performed to removethe material of substrate 102 for the formation of trench 202. In anembodiment, trench 202 has a closed end within the substrate and an openend 204 adjacent a surface 102 a of the substrate 102.

The formation of the buried trench 104 may comprise a filling processfollowed by an etch-back process. The filling process may be performedby depositing a layer 206 of dielectric material over the partiallyfabricated IC 100 a of FIG. 2A such that at least trench 202 may befilled, as shown in FIG. 2B. The deposition of layer 206 may beperformed using any conventional deposition methods suitable fordielectric materials. For example, dielectric materials such as siliconoxide or silicon nitride may be deposited for layer 206 using a chemicalvapor deposition (CVD) or an atomic layer deposition (ALD) process.Following the deposition of layer 206, an etch-back process may beperformed to remove layer 206 from all areas except for a portion 212,as shown in FIG. 2C.

The formation of filled portion 212 may be followed by initiating areshaping of portion 210 of the substrate that surrounds the open end204 of the trench. Initiating the reshaping of portion 210 may includecausing the substrate material surrounding portion 210 to flow and coverthe dielectric layer in the portion 212 and to create the buried trench104 as shown in the example embodiment of FIG. 2D. The reshaping processmay continue to close the substrate area 214 on top of the buried trench104. The reshaping of the substrate area 214 may continue until thesurface 102 a of the substrate 102 is substantially even over the buriedtrench 104, as shown in example embodiment of FIG. 2E.

In an embodiment, the reshaping of the substrate may include usinghydrogen annealing to cause the substrate material to flow. In anembodiment, the hydrogen annealing comprises annealing in temperaturerange of approximately 600° C. to approximately 1150° C. In anembodiment, the hydrogen annealing comprises annealing in pressure rangeof approximately 0.1 Pa to approximately 100 kPa.

It should be understood that the various layers illustrated during theexample fabrication process of IC 100 a are not necessarily drawn toscale. In addition, the above description is meant to provide a generaloverview of select steps involved in forming IC 100 a shown in FIG. 1Aand that, in actual practice, more features and/or fabrication steps maybe performed additionally or alternatively to that described herein toform IC 100 a, as would be understood by one skilled in the art giventhe description herein.

An Example Method for Fabricating an Integrated Circuit According to aSecond Embodiment

FIGS. 3A-3C illustrate cross-sectional views of partially fabricated IC100 a during formation of buried trench 104, according to an embodiment.According to the embodiment, before initiating the reshaping of thesubstrate material surrounding portion 210 of the trench 104, a seedlayer 302 may be formed on the dielectric layer 208.

In an example, embodiment shown in FIG. 3B, seed layers 304 a and 304 bare formed before initiating reshaping of the substrate materialsurrounding portion 210 of the trench 104. Seed layers 304 a may beformed on the dielectric layer 208 according to an embodiment. Seedlayer 304 b may be formed on the surface 102 a of substrate 102 outsidetrench 104.

In an example embodiment shown in FIG. 3C, seed layer 306 may be formedbefore initiating reshaping of the substrate material surroundingportion 210 of trench 104. Seed layer 306 may be formed such that itcovers top of the dielectric layer 208, and sidewall of portion 210 oftrench 104 and top surface 102 a of substrate 102.

A seed layer may comprise a material that helps smooth reshaping or flowof the substrate material surrounding section 210 and closing of opening204 of trench 104. A seed layer may comprise materials containingSilicon or Germanium which won't produce dielectric material. In anembodiment, a seed layer comprises same material as the substratematerial.

It should be understood that the various layers illustrated during theexample fabrication process of IC 100 a are not necessarily drawn toscale. In addition, the above description is meant to provide a generaloverview of select steps involved in forming IC 100 a shown in FIG. 1Aand that, in actual practice, more features and/or fabrication steps maybe performed additionally or alternatively to that described herein toform IC 100 a, as would be understood by one skilled in the art giventhe description herein.

An Example Method for Fabricating an Integrated Circuit According to aThird Embodiment

FIGS. 4A-C illustrate an example fabrication process for forming IC 100b shown in FIG. 1B, according to an embodiment. For the sake ofsimplicity, devices 101 are not shown in the figures for illustratingexample methods of forming a buried trench. In some embodiments, devices101 may be fabricated before forming a buried trench. In some otherembodiments, devices 101 may be fabricated after forming a buriedtrench.

FIG. 4A illustrates a cross-sectional view of a partially fabricated IC100 b after formation of trench 202 in substrate 102. Trench 202 may beformed by methods described with respect to FIG. 2A.

Forming the buried trench 105 may include reshaping portion of thesubstrate surrounding the open end 204 of the trench 202 in FIG. 2A.Reshaping may include causing the portion of substrate materialsurrounding the open end 204 of the trench 202 to flow such that theopening 204 is closed. In an embodiment, hydrogen annealing is used tocause the substrate material to flow.

FIG. 4B illustrates cross-sectional views of partially fabricated IC 100b during formation of buried trench 105 during an embodiment. Aftercausing the substrate material 404 to flow, the embodiment will closethe opening of the trench, such that area 402 is enclosed by substratematerial 404.

FIG. 4C illustrates cross-sectional views of partially fabricated IC 100b after formation of buried trench 104 during an embodiment.

An Example Method for Fabricating an Integrated Circuit According to aFourth Embodiment

FIGS. 5A-5E illustrate an example fabrication process for forming IC 100c, according to an embodiment. In an embodiment, the process shown inFIGS. 5A-5D is used before devices 100 are formed. In anotherembodiment, the process shown in FIGS. 5A-5D is used after devices 100are formed.

FIG. 5A illustrates a cross-sectional view of a partially fabricated IC100 c after formation of trench 202 in substrate 102. Trench 202 may beformed by methods described with respect to FIG. 2A.

Forming the buried trenches 106 may include reshaping portions of thesubstrate at more than one location along the trench 202 shown in FIG.5A. Reshaping may include causing the portion of substrate materialsurrounding a section of the trench 202, for example section 502 shownin FIG. 5B, to flow such that the trench 202 is closed in that portion.

The reshaping of the substrate material surrounding portion 502 of thetrench 202 may continue until buried trench 106 a is formed, as shown,for example, in FIG. 5C. In an embodiment, another buried trench abovethe buried trench 106 a may be created by reshaping substrate materialfor example around portion 504 of the trench 202. The reshaping of thesubstrate material may continue until the buried trench 106 b is formed,as shown, for example, in FIG. 5D.

Another buried trench above the buried trench 106 b may also be formedby closing the opening 204 of the trench 202 in a manner similar to theprocess explained in FIGS. 4A-C above, as shown, for example, in FIG.5D. The reshaping of the substrate material may continue until theburied trench 106 c is formed, as shown, for example, in FIG. 5E.

In an embodiment, hydrogen annealing is used to cause the substratematerial to flow. In another embodiment, buried trenches 106 may beempty of any solid material. The buried trenches 106 may, for example,contain air.

It should be understood that the various layers illustrated during theexample fabrication process of IC 100 c are not necessarily drawn toscale. In addition, the above description is meant to provide a generaloverview of select steps involved in forming IC 100 c shown in FIG. 1Cand that, in actual practice, more features and/or fabrication steps maybe performed additionally or alternatively to that described herein toform IC 100 c, as would be understood by one skilled in the art giventhe description herein.

Example Steps for Fabricating an Integrated Circuit According to a FirstEmbodiment

FIG. 6 illustrates a flowchart for a method 600 of fabricating an IC,e.g., IC 100 a shown in FIG. 1A, according to an embodiment. Solely forillustrative purposes, the steps illustrated in FIG. 6 will be describedwith reference to example fabrication process illustrated in FIGS.2A-2E. It is to be appreciate not all steps may be required, nor occurin the order shown.

In step 602, trench 202 may be formed in the substrate 102, as shown inFIG. 2A, by a dry etch process such as, but not limited to, reactive ionetching (RIE) to remove the material of substrate 102, according to anembodiment.

In step 604, trench 202 may be filled by depositing a layer 206 ofdielectric material such as silicon oxide or silicon nitride. Thedeposition of layer 206 may be performed using, for example, a CVD or anALD process. In step 606 an etch-back process is used to remove a layerfrom all areas except for portion 208, as described above with referenceto FIG. 2C.

In step 608 the open portion 204 of the trench is closed by causing thesubstrate material surrounding it to flow by, for example, Hydrogenannealing.

It should be noted that, although the above method description andrelated figures describe fabricating only one arrangement of buriedtrench 104 interposed between adjacent devices 101 for the sake ofsimplicity. However, as would be understood by a person of skilled inthe art based on the description herein, the above steps may be appliedto fabricate any number of such arrangements with devices and trenchessimilar to devices 101 and trench 104, respectively.

Those skilled in the relevant art(s) will recognize that the abovemethod 600 may additionally or alternatively include any of the steps orsub-steps described above with respect to FIGS. 2A-2E, as well as any oftheir modifications. Further, the above description of the examplemethod 600 should not be construed to limit the description of IC 100 adescribed above.

Example Steps for Fabricating an Integrated Circuit According to aSecond Embodiment

FIG. 7 illustrates a flowchart for a method 700 of fabricating an IC,e.g., IC 100 b shown in FIG. 1B, according to an embodiment. Solely forillustrative purposes, the steps illustrated in FIG. 7 will be describedwith reference to example fabrication process illustrated in FIGS.4A-4C. It is to be appreciate not all steps may be required, nor occurin the order shown.

In step 702, trench 202 may be formed in the substrate 102, as shown inFIG. 2, by a dry etch process such as, but not limited to, reactive ionetching (RIE) to remove the material of substrate 102, according to anembodiment. In step 704 the open end 204 of the trench is closed to formburied trench 105. Closing of the open end of the trench may be done bycausing the substrate material surrounding it to flow, for example byHydrogen annealing.

At step 706, memory cell devices 101 are formed on both sides of thetrench 202.

It should be noted that, although the above method description andrelated figures describe fabricating only one arrangement of buriedtrench 104 interposed between adjacent devices 101 for the sake ofsimplicity. However, as would be understood by a person of skilled inthe art based on the description herein, the above steps may be appliedto fabricate any number of such arrangements with devices and trenchessimilar to devices 101 and trench 105, respectively.

Those skilled in the relevant art(s) will recognize that the abovemethod 700 may additionally or alternatively include any of the steps orsub-steps described above with respect to FIGS. 4A-4C, as well as any oftheir modifications. Further, the above description of the examplemethod 700 should not be construed to limit the description of IC 100 bdescribed above.

It is to be appreciated that the Detailed Description section, and notthe Summary and Abstract sections (if any), is intended to be used tointerpret the claims. The Summary and Abstract sections (if any) may setforth one or more but not all embodiments of the present disclosure ascontemplated by the inventor(s), and thus, are not intended to limit thepresent disclosure or the appended claims in any way.

Embodiments have been described herein with the aid of functionalbuilding blocks illustrating the implementation of specified functionsand relationships thereof. The boundaries of these functional buildingblocks have been arbitrarily defined herein for the convenience of thedescription. Alternate boundaries can be defined as long as thespecified functions and relationships (or equivalents thereof) areappropriately performed. Also, alternative embodiments may performfunctional blocks, steps, operations, methods, etc. using orderingsdifferent than those described herein.

The breadth and scope of the present disclosure should not be limited byany of the above-described embodiments, but should be defined only inaccordance with the following claims and their equivalents.

1-4. (canceled)
 5. An integrated circuit (IC) comprising: a substrate; a first device and a second device formed on a surface of the substrate, the first device and the second device each comprising a gate structure; and an isolator arranged to isolate the first device and the second device from one another, wherein the isolator comprises at least one cavity buried in the substrate, and wherein the isolator is positioned between the first and second devices.
 6. The IC of claim 5, wherein the at least one cavity is filled with a dielectric material.
 7. The IC of claim 6, wherein the dielectric material is air.
 8. The IC of claim 6, further comprising a seed material disposed between a top of the dielectric material and the surface of the substrate, wherein the seed material is configured to smooth a reshaping of the substrate over the isolator.
 9. The IC of claim 8, wherein the seed material comprises silicon or germanium.
 10. The IC of claim 5, wherein a vertical cross-section of the at least one cavity has a rectangular perimeter.
 11. The IC of claim 5, wherein a vertical cross-section of the at least one cavity has a height greater than a width.
 12. The IC of claim 5, wherein the isolator comprises at least two cavities buried in the substrate.
 13. The IC of claim 12, wherein the at least two cavities are aligned along a line that is substantially perpendicular to the surface of the substrate.
 14. An integrated circuit (IC) comprising: a substrate; a plurality of devices formed on a surface of the substrate; and an isolation region arranged to isolate at least a first device and a second device of the plurality of devices from one another, wherein the isolation region: comprises at least one cavity buried in the substrate, wherein the cavity is filled with dielectric material; and is positioned between the at least first and second devices.
 15. The integrated circuit of claim 14, wherein the dielectric material comprises oxide or nitride.
 16. The integrated circuit of claim 14, wherein the dielectric material comprises air.
 17. The integrated circuit of claim 14, wherein the isolation region comprises at least two cavities.
 18. The integrated circuit of claim 17, wherein the at least two cavities are aligned along a line that intersects with the surface of the substrate.
 19. The integrated circuit of claim 14, further comprising a seed material disposed between a top of the dielectric material and the surface of the substrate, wherein the seed material is configured to smooth a reshaping of the substrate over the isolation region.
 20. The integrated circuit of claim 19, wherein the seed material comprises silicon or germanium.
 21. An apparatus comprising: a substrate: and an isolator disposed to isolate a first device and a second device formed on a surface of the substrate, wherein the isolator comprises at least one cavity filled with dielectric and buried in the substrate, and wherein the isolator is positioned between the first device and the second devices.
 22. The apparatus of claim 21, wherein the first device and second device each comprise a gate structure.
 23. The apparatus of claim 21, further comprising a seed material disposed between the dielectric and the substrate, wherein the seed material is configured to smooth reshaping of the substrate over the isolator.
 24. The apparatus of claim 23, wherein the seed material comprises silicon or germanium. 